1. Technical Field
This disclosure relates to semiconductor fabrication, and more particularly, to method for reducing hot carrier effects in buried channel metal oxide semiconductor field effect transistor (MOSFET) solid state devices.
2. Description of the Related Art
A dynamic random access memories (DRAMs) include an array area which typically has transistors and capacitors. The capacitors are typically configured to store a charge, which can be accessed by appropriate support circuitry associated with the DRAM. Typically, the array circuitry and the support circuitry of the DRAM are located in different areas of the integrated circuit (IC). Although transistors are present in both the array area and the support area of the DRAM, N-FETs (N-channel Field Effect Transistors) are typically employed in the array area, while P-FETs (P-channel Field Effect Transistors) are generally employed in the support circuitry area. The transistors are typically implemented in wells, which are created in the substrate of the integrated circuit. These wells are separated, in some circuits, by shallow trench isolation structures.
Referring to FIG. 1, a region between a transistor 101 and a shallow trench isolation (STI) structure 100 is illustratively shown. STI 100 and transistor 101 are created in a silicon substrate 102. Transistor 101 includes a gate dielectric layer 110 formed on a surface 113 of substrate 102, and a gate conductor 112 formed on gate dielectric layer 110. Transistor 101 includes a junction 114, which abuts STI 100. STI 100 typically includes an oxide layer 120, a nitride layer or liner 122 and an oxide fill material 124. STI 100 electrically isolates a sidewall of transistor 101.
When gate conductor 112 is activated, an electric field, E, is applied to junction 114 as indicated by electric field lines 126 and conduction occurs through junction 114. STI 100 is provided to electrically isolate junction 114 from other devices formed on substrate 102. However, due to the isolation process, a localized area 130 along STI 100 is more sensitive to hot carrier damage. Area 130 in this case includes a divot 128 and nitride layer 122 which induces charge trapping and causes localized damage during operation of transistor 101 due to hot carrier effects. Area 130 is also responsible for parasitic leakage in transistor 101.
It is difficult to control the depth of divot 128 created by an etch process employed to strip a pad nitride layer (not shown). Since the gate conductor 112 (e.g., polysilicon) is subsequently deposited into this divot region 128, the variable depth of divot region 128 leads to a variable amount of polysilicon wrapped around the gate of transistor 101. This affects control of the threshold voltage of the gate to be formed, thereby degrading performance of transistor 101 during operation. However, the proximity of nitride liner 122 to the transistor channel disadvantageously exacerbates the hot carrier reliability problem for P-FET transistors. Hot carrier reliability problems are caused when nitride liner 122 traps or collects charge that should traverse the P-FET channels located near STI 100. Nitride liner 122 reduces dislocation density in substrate 102. As can be appreciated by those skilled in the art, hot carrier reliability problems increase power consumption of the P-FET transistors and, in some cases, may lead to incorrect timing of the circuitry.
The activation of a parasitic sidewall device in area 130 during hot carrier stresses is one of the main concerns in Buried Channel PMOSFETs technologies with STI isolation. For example, the enhanced hot carrier sensitivity is a limiting factor for an aggressive burn-in strategy (for testing manufactured chips) and constrains the device/circuit design. This phenomenon can take place in buried channel PMOS devices controlled by electron trapping localized in the gate-sidewall-drain region, as indicated in FIG. 1, and results in an increase in the device threshold voltage, Vth, (i.e., the device is easier to turn on).
The activation of a parasitic sidewall device in area 130 increases in buried channel PMOS devices due to hot carrier aging. This has been established to be the main contributor to the increase in the chip stand-by current in single work-function DRAM technologies with STI with nitride liner isolation.
The presence of nitride liner 122 increases the electron trapping efficiency in a localized region around the nitride liner 122 and below divot 128. If the point of electron injection along the sidewall is close to area 130, the device will be more sensitive to the parasitic sidewall activation. This effect can be also produced by any process that can produce a localized region of enhanced electron trapping.
Therefore, a need exists for reducing hot carrier reliability problems in semiconductor devices by providing a buried channel, which avoids areas of high hot carrier sensitivity.